FIG. 15 is a diagram illustrating an example of the constitution of the memory cell in a general 1-port SRAM (static random-access memory). The memory cell shown in FIG. 15 has six transistors (n-type MOS transistors Qn1–Qn4, p-type MOS transistors Qp1, Qp2). Among said transistors, p-type MOS transistor Qp1 and n-type MOS transistor Qn3 form inverter circuit IV1, and p-type MOS transistor Qp2 and n-type MOS transistor Qn4 form inverter circuit IV2. The inputs and outputs of inverter circuits IV1 and IV2 are connected in the form of a ring, and the signal levels of connecting nodes N0 and N1 are held at complementary levels. That is, one node is held at the high level, while the other node is held at the low level. Due to this signal holding function, 1-bit information is stored in inverter circuits IV1 and IV2.
Node N0 is connected via n-type MOS transistor Qn1 to bit line BL. Node N1 is connected via n-type MOS transistor Qn2 to bit line XBL. The gates of n-type MOS transistors Qn1 and Qn2 are connected to word line WL, and the transistors are turned on when word line WL is at the high level and off when the word line is at the low level. When the monitored data of the memory cell is held, word line WL is set to the low level. As a result, nodes N0, N1 and bit lines BL, XBL are separated from each other, and the signal levels of nodes N are held. On the other hand, when the memory cell is to be accessed, word line WL is set to the high level. As a result, node N0, N1 are connected to bit lines BL, XBL, and, via these bit lines, data can be written to or read from the memory cell.
When data is to be written to the memory cell, the complementary signals corresponding to the write data value are output to bit line pair BL, XBL. That is, signals are output to so that one of bit lines BL, XBL is at the high level and the other is at the low level. The levels of nodes N0, N1 are set corresponding to the complementary signals. Also, when data is to be read from the memory cell, word line WL is set to the high level while bit lines BL, XBL are set to the high impedance state. As a result, the signal levels of nodes N0, N1 are displayed on bit lines BL, XBL. In this way, in the memory cell shown in FIG. 15, data write/read is performed via the common bit line pair BL, XBL.
On the other hand, in the 2-port SRAM, reading and writing are performed using independent word lines and bit lines. Consequently, it is possible to perform parallel write and read operations for memory cells having different addresses. FIG. 16 is a diagram illustrating an example of the constitution of the memory cell in a general 2-port SRAM. Like the memory cell shown in FIG. 15, the memory cell shown in FIG. 16 also has six transistors. It also has six additional transistors (n-type MOS transistors Qn5–Qn8, p-type MOS transistors Qp3, Qp4).
The connecting configuration and operation of transistors Qn1–Qn4, Qp1, Qp2 are the same as those of the memory cell shown in FIG. 15. The terminal of n-type MOS transistor Qn1 on the bit line side is connected via n-type MOS transistor Qn5 to ground G. The bit-line-side terminal of n-type MOS transistor Qn2 is connected via n-type MOS transistor Qn6 to ground G. Write bit line WBL is connected to the gate of n-type MOS transistor Qn5, and write bit line XWBL is connected to the gate of n-type MOS transistor Qn6. Also, the gates of transistors Qn1 and Qn2 are connected to write word line WWL. Transistors Qn7, Qn8, Qp3, Qp4 form a circuit for outputting the memory data to read bit line RBL. N-type MOS transistor Qn7 and p-type MOS transistor Qp3 form inverter circuit IV3. Inverter circuit IV3 inverts the signal of node N1 and outputs it to read bit line RBL. N-type MOS transistor Qn8 is inserted between said inverter circuit IV3 and ground G. P-type MOS transistor Qp4 is inserted between inverter circuit IV3 and power source line Vcc. The gate of n-type MOS transistor Qn8 is connected to read word line RWL, and the gate of p-type MOS transistor Qp4 is connected to read word line XRWL. Said n-type MOS transistor Qn8 and p-type MOS transistor Qp4 are both turned on or off corresponding to the complementary signals input to the read word line pair (RWL, XRWL).
When data is written to the memory cell shown in FIG. 16, the complementary write signal is supplied to the write bit line pair WBL, XWBL while write word line WWL is set to the high level. Corresponding to said write signal, one of n-type MOS transistors Qn5 and Qn6 is turned on, and, via the on transistor, node N0 or N1 is pulled down to the zero level. In this way, the levels for node N0 and N1 are set corresponding to the write signal.
On the other hand, when data is to be read from the memory cell, read word line RWL is set to the high level, while read word line XRWL is set to the low level. As a result, both n-type MOS transistor Qn8 and p-type MOS transistor Qp4 are turned on, and inverter circuit IV3 works and outputs NOT signal of node N1 to read bit line RBL.
In the memory cell design, the most important factors to consider are guaranteeing both “writing facility” and “stored data stability.” The first property is known as write margin (hereafter referred to as WM), and the second property is known as static noise margin (hereafter referred to as SNM). As will be explained below, these properties contradict each other. That is, enhancing one requires sacrificing the other, which is undesirable.
FIG. 17 illustrates the operation when the stored data in the memory cell shown in FIG. 15 is damaged. FIG. 17(A) shows the state in which n-type MOS transistors Qn1 and Qn2 are turned on while bit lines BL, XBL are precharged. FIG. 17(B) shows the voltage waveforms of the various portions in this case. Usually, in data read mode, the bit line is precharged to the high level. Also, in data write mode, the bit lines connected to the memory cells that are not write objects are precharged to the high level. As shown in FIG. 17(A), when n-type MOS transistors Qn1 and Qn2 are turned on while the bit line is precharged, current flows into the node at the low level from the bit line, and the voltage of this node rises.
In the example shown in FIG. 17, during a normal read operation, as the voltage on word line WL (curve C1) changes to the high level, and n-type MOS transistors Qn1 and Qn2 are turned on, although there is a certain rise in the voltage of node N1 (curve C4) held at the low level, it does not reach the state of level inversion, and the voltage of node N2 (curve C2) is held at the high level. Consequently, after n-type MOS transistors Qn1 and Qn2 return to the off state, node N0 goes to the high level, and node N1 goes to the low level.
In the example shown in FIG. 17, when data damage takes place, as n-type MOS transistors Qn1 and Qn2 are turned on, along with the rise in voltage at node N1 (curve C5), the logic of inverter IV1 is inverted, and the voltage at node N2 (curve C3) decreases. As a result, when word line WL returns to the low level, node N0 goes to the low level, and node N1 goes to the high level. Thus, in order to increase the SNM such that it is difficult for said data damage to take place, within the range of meeting the specification for the data read access time, it is preferred that the drivability of n-type MOS transistors Qn1 and Qn2 be as low as possible, and that the current sourced by the bit line be low.
FIG. 18 illustrates a data write failure to the memory cell shown in FIG. 15. FIG. 18(A) illustrates the state in which n-type MOS transistors Qn1 and Qn2 are turned on when the write signal has been input to bit lines BL, XBL. FIG. 18(B) illustrates the voltage waveforms of the various portions in this case. In the example shown in FIG. 18, during a normal write operation, as n-type MOS transistors Qn1 and Qn2 are turned on, the voltage at node N0 (curve C7) held at the high level is pulled down by the low level voltage of bit line BL, while the voltage at node N1 (curve C9) held at the low level is pulled up by the high level voltage of bit line XBL. Due to these voltage changes, a level inversion takes place, so that node N0 goes to the low level, and node N1 goes to the high level. In the example shown in FIG. 18, when a data write defect takes place, the decrease in the voltage of node N0 (curve C8) and the rise in the voltage of node N1 (curve C10) are insufficient. Consequently, no level inversion takes place during the on period of n-type MOS transistors Qn1 and Qn2. Thus, the rewrite operation of node N0 and N1 is performed in the same way as described above.
In order to increase the WM so that it is difficult for said write defect to take place, it is preferred that the drivability of n-type MOS transistors Qn1 and Qn2 be increased as much as possible, and the current from the bit line be as high as possible. Consequently, when the drivability of n-type MOS transistors Qn1 and Qn2 is decreased to improve the SNM, the WM deteriorates. On the other hand, when the drivability of said transistors is increased to improve the WM, the SNM deteriorates. That is, the SNM and WM contradict one another. Consequently, when designing memory, it is necessary to adjust the size, etc. of n-type MOS transistors Qn1 and Qn2 and other transistors so that the required specifications for both are met.
However, in recent years, with progress in processing technology for low power, low-threshold transistors, it has become difficult to meet these contradictory requirements for the SNM and WM at the same time by this means of adjusting the size of transistors, etc. On the other hand, in the 2-port type memory cell shown in FIG. 16, inverter circuit IV3 is used for reading data so that the read bit line and memory nodes N0, N1 are not directly connected to each other. Also, for the memory cell that is not the write object during the data write operation (when word line WWL is at the high level), write bit lines WBL and XWBL are set to the low level. Consequently, both n-type MOS transistors Qn5 and Qn6 are turned on, and little current flows into node N0 and N1. Consequently, in terms of the SNM, the 2-port type memory cell shown in FIG. 16 is better than the 1-port type memory cell shown in FIG. 15. However, in the memory cell shown in FIG. 16, when a write is to be performed, only the node on one side is pulled down to the low level, while the other node is set to the high impedance state. Consequently, compared with the scheme shown in FIG. 15 in which both nodes N0 and N1 can be driven, the memory cell shown in FIG. 16 has a low ability to be written to, so that the WM performance deteriorates. Also, the current for pulling down the potential of node N0 and N1 to the low level flows through 2-stage tandem-connected transistors Qn1 and Qn5, Qn2 and Qn6 to ground G. Consequently, this point also leads to degradation in WM performance. In particular, when the power voltage and transistor threshold further decrease in the future, the impedance of the tandem-connected transistors will significantly further decrease the drivability.
The purpose of the present invention is to solve the problems of the prior art by providing a static memory cell that can suppress the degradation of the SNM and improve the WM, and an SRAM device containing said memory cells in order to improve the reliability.